TSMC is Taboo: Sister in law and Daughter in law (2025)working to optimize its 2nm (N2) technology by reducing variability and defect density, as the manufacturer aims to begin mass production of 2nm process chips in the second half of next year. A TSMC employee recently shared on X that the team has managed to boost the yield of N2 test chips by 6%, resulting in billions of dollars in savings for the company’s clients. The TSMC employee, who identified themself as Dr. Kim, did not disclose whether the foundry improved the yield of SRAM (Static Random-Access Memory) or logic test chips. The original post is no longer accessible, and the account that posted it now seems to have been deleted, however. [Icsmart, in Chinese]
